1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method.
2. Related Art of the Invention
In recent years, for the purpose of concurrently promoting densification of semiconductor elements and higher pin counts of electrode terminals, efforts have been made toward pitch reduction and area reduction in electrode terminals of semiconductor elements.
Typically, with flip-chip mounting, mounting is performed by forming a projecting electrode such as a solder bump on an electrode terminal of a semiconductor element such as an LSI, and pressure-welding and heating the semiconductor element faced downward with respect to a connecting terminal of a mounting board in order to perform bump connection.
However, since advances in pitch reduction have been significant, conventional means in which electrode terminals are peripherally arranged may result in an occurrence of a short-circuit between electrode terminals or an occurrence of a bad connection or the like due to a difference in coefficients of thermal expansion between a semiconductor element and a mounting board. In consideration thereof, a method of increasing the pitch between electrode terminals by arranging electrode terminals in an area array has been adopted. However, recent advances in pitch reduction have been significant even in area arrays.
As a method of forming a solder bump, a method has been adopted where solder is first formed on an electrode by screen printing, a method using a dispenser, or electrolytic plating, and then heated to a solder melting temperature or higher by a reflow furnace to form a projecting solder bump.
However, due to recent realizations in even narrower pitches of solder joints and smaller gaps between semiconductor elements and substrate electrodes, problems have emerged, such as a deformation of solder melted in a heating process during flip-chip mounting and a generation of a solder bridge defect where solder bumps become connected to each other due to surface tension of the solder.
A method of configuring a bump in two layers has been proposed in order to respond to such demands.
For example, there is a method of forming an insulating film containing metallic particles so as to cover a surface of a projecting electrode made of gold or copper (for example, refer to Japanese Patent Laid-Open No. 2003-282617). According to this method, electrical continuity can be established by a force in a compression direction due to cure shrinkage of an encapsulation resin injected between a semiconductor element and a substrate without having the insulating film or the projecting electrode melt during flip-chip mounting. As a result, bridge generation can be prevented and pitch reduction can be accommodated.
However, since recent demands for pitch reduction of pitches between electrodes are very strenuous, with a connection topology where continuity is secured solely by contact without any diffusion bonding between metallic particles and metallic electrodes as is the case with Japanese Patent Laid-Open No. 2003-282617, a reduction in electrode area obviously reduces the number of conductive particles interposed between electrodes and creates a problem of higher connection resistance and greater signal transmission loss.
In consideration thereof, a method has been adopted in which a bump is configured in two layers, namely, a lower layer metal and an upper layer metal, and the upper layer metal made of solder is formed on top of the lower layer metal made of high-melting point metal (for example, refer to Japanese Patent Laid-Open No. 9-97791).
FIG. 7 is a cross-sectional view conceptually illustrating a semiconductor device according to an embodiment described in Japanese Patent Laid-Open No. 9-97791.
An electrode 11a made of a high-melting point metal is formed on a semiconductor element 11, and solder 13 is formed on the electrode 11a. By positioning the electrode 11a on the semiconductor element 11 so as to oppose an electrode 12a formed on a circuit board 12, mounting the semiconductor element 11 onto the circuit board 12, and applying heat and pressure, entire surfaces of the electrode 11a on the semiconductor element 11 and the electrode 12a on the circuit board 12 are diffusion-bonded by the solder 13.
According to this method, the amount of solder can be reduced compared to a bump made of a single solder layer, the amount of solder collapse in a planar direction during flip-chip mounting can be reduced, and generation of a solder bridge can be prevented. In addition, since the solder and the board electrode are diffusion-bonded, connection resistance can be kept low and an increase in signal transmission loss can be avoided.